1. Field of the Invention
This invention relates to differential amplifiers or comparator circuits.
2. Brief Description of the Prior Art
Differential amplifiers or comparators generally require high gain and high frequency response. The frequency response of a differential amplifier or comparator circuit is inversely proportional to the differential gain. As shown in FIG. 1, which is a typical basic prior art differential amplifier circuit, the differential amplifier frequency response or bandwidth is dominated by the RC time constant which is the product of the resistance of resistor R1 or R2 connected to a collector (or drain) of the differential transistor pair Q1 or Q2 and the lumped capacitance of the collector (or drain in the case of an MOS embodiment) nodes. The capacitance of the collector nodes, C, is dominated by the collector to substrate capacitance and the collector to base capacitance. The capacitance, C, is also dependent upon the semiconductor process used. Therefore, the capacitance C of the differential amplifier is fixed and cannot be reduced. The differential gain of the amplifier is proportional to the resistance of resistor R1 or R2 divided by the differential pair emitter (or source in the case of an MOS embodiment) resistance. The higher the resistance value of resistors R1 and R2, the greater the gain. Also, the lower the resistance value of resistors R1 and R2, the higher the frequency response. Therefore the performance of a differential amplifier is the result of a trade-off between frequency response and differential gain. To increase the gain of the amplifier, the resistance values of resistors R1 and R2 must be increased and to increase the frequency response, the resistance values of resistors R1 and R2 must be reduced.
Several differential amplifier stages can be cascaded to increase the gain. If there are, for example, three stages and the gain of each stage is, for example, 10, then the gain of the circuit is the product of the gain for each stage or 1000. Cascading gain stages can provide higher gains but is more susceptible to noise and increase power dissipation. Timing errors are also introduced when the differential input voltage is reduced (overdrive).
Transistors Q1 and Q2 do not completely switch, where the current supplied by transistor Q3 is shared by transistors Q1 and Q2. The voltage across the resistors R1 and R2 in the first stage does not reach full amplitude because the current is being shared by transistors Q1 and Q2. The differential voltage takes much longer to pass through the threshold because the RC effect is still present, but at a lower amplitude. The lower differential output causes the next differential pair to share current longer and switch at a slower rate as well. At these lower differential input voltages, noise can be introduced in the first two cascaded stages. Inductance of the package leads for power, ground and input leads can introduce noise on the die. Noise can be introduced by power and ground ringing, noisy substrate coupling to the signal paths or crosstalk between signals, causing positive and/or negative parasitic feedback. Positive feedback can cause frequency dependent timing errors and negative feedback can cause low level oscillations. Higher gain in the first stage will reduce these noise related errors.
Both high gain and high frequency response of differential comparator circuits is required for analog to digital conversions. This includes high speed comparators for logic threshold conversions, digital input and output buffers, flash converters and successive approximation analog to digital converters.
A circuit which has been used to improve frequency response involves the addition to the differential amplifier of FIG. 1 of schottky diodes (D1, D2) with a series resistor R4 across the differential output resistors R1 and R2 as shown in FIG. 2. The series resistor R4 is chosen to be 1/2 of R1 or R2 such that the high and low state is centered around the threshold voltage. The diodes D1, D2 are 0 volts biased at the threshold of the amplifier such that the gain is not reduced by the added circuit. However, the schottky diodes D1, D2, become forward biased through the series resistor R4 once the differential output has crossed through the threshold. With the diodes D1, D2 forward biased, the RC resistance is reduced to R1 in parallel with the series resistor R4+resistor R2 or 0.6.times.R1. The reduced R improves the rise time to 2.2.times.(0.6.times.R).times.C or 1.32 RC. This is a significant improvement, but the capacitance, C is assumed to be constant. Actually, the addition of the diodes adds a significant amount of capacitance (about 25% or more). Therefore, the rise time is T.sub.r =1.32.times.RC.times.(1.25) or 1.65.times.RC. This is still a significant improvement over 2.2.times.RC.
It is the goal to further improve one or both of the frequency response and the gain of a differential amplifier without affecting the other or by affecting the other to a lesser extent than in the prior art, thereby diminishing or eliminating the trade-off.